Imagine two micrographs side-by-side, one of a transistor from an Intel286 microprocessor from 1982 and one of a transistor from the brains ofthe latest smartphone. While they appear quite similar, the new one is100 times smaller.
But conventional transistor scaling is reaching its limits. Beyond the 22nm technology node – sometime in the middle of this decade – traditionaltwo-dimensional, or planar, transistors may be a thing of the past. Tocontinue the incredible advances in speed, battery life and cost, thetechnology must change. Two new approaches are being considered:three-dimensional transistors and enhancements to planar transistors.
I recently attended a forum that Applied Materials hosted in SanFrancisco where a panel of experts debated the relative merits of theseapproaches. Speaking to an audience of over 200 technologists, the panel included experts from leading chip companies: GlobalFoundries, IBM, Qualcomm, Samsung and STMicroelectronics and was moderated by Professor Yuan Taur from U.C. San Diego.
The most serious shortcoming of current planar transistors is leakagecurrent, a major source of wasted battery power. The 3D approach splitsthe transistor gate into multiple parts (multi-gate), allowing more effective suppression of the leakage current. 3Dtransistors also tend to be taller and narrower than planar ones,allowing more transistors to be packed into the same area on the chip.
Witek Maszara, principal member of technical staff at GlobalFoundries, Inc.came out in favor of 3D technology. He believes that 3D transistorsoffer the lowest power density, key to giving mobile devices theendurance to match their performance. Ghavam Shahidi, Fellow in theResearch Division at IBM Corp., agreed that 3D transistors arepromising, but will be difficult to make in high-volume manufacturingand ultimately will also suffer leakage problems, limiting theirlong-term viability.
Going a step further, Thomas Skotnicki,Fellow and director of Advanced Devices at STMicroelectronics assertedthat 3D transistors will never be the best choice for low powerapplications because the structure of 3D transistors prevents the use of “body bias” which can cut leakage in half during idle periods.
Instead, Shahidi and Skotnicki favor an enhanced planar transistor approach,which aims to overcome existing scaling bottlenecks while retaining thesame basic physical arrangement. In this technique, a very thin channelof “fully-depleted,” or pure, silicon is placed over a layer ofinsulating material – therefore called fully-depletedsilicon-on-insulator (FD-SOI). By isolating the channel from the underlying silicon wafer in this way, leakage current can be greatly reduced and remarkable switching speedsachieved.
Dong Kyun Sohn, vice president in charge of the logiclab at Samsung Microelectronics’ R&D Center said that his company is still evaluating both approaches. The winner, he said, must balancedesign restrictions, cost, performance and scalability to achieve thebest overall performance.
Offering a different perspective,Geoffrey Yeap, vice president in charge of silicon technology atQualcomm, Inc. pointed out that every part of a smartphone, theprocessor, the modem, the software etc., makes different tradeoffs toadd up to the best overall user experience. The key to success for afabless company such as Qualcomm is “holistic co-design” where theyengage multiple steps up and down the value chain to deliver “More thanMoore” performance.
The cost of developing new technology causeschipmakers to choose the evolutionary over the revolutionary. Novel 3Dtechnologies will require time-consuming and expensive development tobring to high-volume manufacturing. FD-SOI transistors, on the otherhand, are structurally similar to today’s transistors and “only” require the refinement of existing techniques to implement. The challenges arestill significant – evenly depositing a channel just a few atoms thickacross a 300mm diameter wafer is not an easy task – but these arechallenges the industry has historically excelled at.
Did theaudience agree with the panel’s conclusions? Asked which technologywould be pre-eminent in 2015, a show of hands declared FD-SOI the clearfavorite, with only a few votes for 3D multi-gate. Interestingly, asignificant number believes conventional planar construction can defendits incumbent position, possibly through design co-optimization and 3Dchip stacking.
And beyond this decade? The experts spoke of carbon nanotubes, nanowires and quantum dots. Clearly, the pursuit of Moore’s Law may take us in some very interesting new directions – at least in theory.