The Era of Nanoscale Chip Wiring
This TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with copper, all the way to the bottom, with no gaps or voids. This was achieved using Applied’s revolutionary copper reflow technology. For a primer on how interconnects are made and how copper reflow works, see this video.
What does this mean? The significance of this image is that it verifies the breakthrough capability of reflow to push the boundaries of interconnect technology beyond the 20nm technology node. Without reflow technology it’s extremely difficult, even improbable to achieve void-free copper interconnect wiring as the industry moves towards single digit technology nodes. Why does this matter? Because at these advanced nodes, a single tiny void in the more than 60 miles of wiring needed to connect billions of transistors can render a chip useless.
To successfully fill and create reliable interconnect structures, a continuous and conformal copper seed layer is essential. Reflow technology enables this for the wiring seed layer, using capillary action to draw down the deposited copper into even the smallest features, filling from the bottom upwards to enable rapid, void-free fill. Filling the bottom of the trench is the difficult part. Filling the rest of the structure, using electrochemical deposition, is (relatively) straightforward.
The great thing about capillary action is that the effect becomes stronger as features get smaller. So, as far as we can see, reflow has no foreseeable node limit. It’s always good to overcome a roadblock to continuing Moore’s Law. Solving a recurring problem once and for all is even better.
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