In Focus: 3D-IC & TSV Technology
Improved performance, reduced timing, reduced power consumption and device scaling attributes are key driving forces for the adoption of new microchip technology for mobile devices referred to as 3D integrated circuits (ICs) and through silicon via (TSV) interconnects. Reducing power consumption leads to the benefits of less heat generation, extended battery life, and a lower cost of operation.
TSVs are essentially vertical holes etched or laser drilled into in silicon wafers and filled with copper, which enable communication between vertically stacked ICs. The technology allows for circuit designers to place stacks of memory chips on top of an application microprocessor chip in order to significantly increase memory bandwidth and reduce power consumption, which are key issues for next-generation mobile devices such as smartphones and tablets. At leading-edge chip node sizes, the adoption of 3D stacking of ICs is increasingly being considered as an alternative to traditional technology node scaling at the transistor level, according to Moore’s Law. TSV technology is leading to major innovations in how chips are packaged as well.
The microchip design community and the manufacturing equipment companies are championing TSV technology at current conferences and trade shows for the purpose of accelerating their transition into production for a wide variety of applications. One of first major goals is to connect graphics memories to graphics processors in mobile systems. Integrated device manufacturers such as Samsung Electronics, which is a major Apple chip supplier for iPads and iPhones, are evaluating TSVs for coupling high-bandwidth dynamic random access memory (DRAM) chips with processor chips. Essentially of the most advanced microchip technology companies have active programs focused on TSV development.
Equipment and materials companies first implemented TSVs for CMOS image sensors, which are the components that enable mobile devices like cell phone cameras. Obtaining the bandwidth increases promised by TSVs is going to be a major interconnect design optimization challenge, as about 10 percent of the typical chip die area is consumed by the vertical interconnects. Even though performance gains in device functionality will be realized, TSVs will still be incorporating copper, as in current interconnects, with an upper limit in frequency (access speed) of approximately 1GHz for a typical 5µm-diameter TSV.
For mobile devices with limited power consumption requirements, TSVs are being deemed the best option to connect a graphics/video processor to several layers of graphics memory, where 12.8 GB/s of bandwidth is needed between the processor and DRAM memory for high-definition video. A conventional HD video solution without TSV technology would require high-frequency operation with over 2,000 I/O pins on a chip, which would severely limit any current battery-operated system.
The global 3D-IC and TSV market is predicted to grow at a combined annual growth rate (CAGR) of 16.9 percent from $2.21B in 2009 to $6.55B in 2016, according to a recent report by research firm, Markets and Markets. This report entitled, “Three-dimensional Integrated Circuit & Through-Silicon Via Interconnects Market – Global Forecast & Trend Analysis (2011-2016)” reveals that the companies in this market need to efficiently balance their expenditure between capacity expansion and technology advancement for capitalizing on this emerging growth opportunity for next-generation mobile devices and beyond.
Brian Coppa, Ph.D., has authored many pending U.S. patents,international peer-reviewed journal articles, and industry analysespublications concerning electronic materials and devices and greentechnology, which have received numerous prestigious citations andgarnered numerous invited presentations across the U.S. He is a leadingsenior consultant for GLG Inc. regarding alternative energy andmicroelectronic applications.
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