As the need for clean energy increases, engineers are working toexpand production and improve the efficiency of crystalline silicon(c-Si) solar factories. Five years ago, a 30 MW solar fab was acompetitive size. Now, companies routinely plan 300 MW-scale fabs, andsome are considering fabs on the scale of 3 GW over the next few years. A key driver in this increase in fab scale is the goal of producing solar modules at a cost of less than US$1 per watt.
This week we arefeaturing a three part series that looks at the interrelated buildingblocks that are key contributors to meeting this goal for c-Si PV:
- Higher Efficiency Cells
- Thinner Wafers and Higher Throughputs
- Advances in Automation
Higher Efficiency Cells
One approach to increasing cell efficiency is “selective emitter” technology in which the conductance of the emitter– i.e. the n-typephosphorous-containing region on the cell front surface – is decreasedover much of the cell area so as to increase photocurrent generation and is selectively increased under the front metal grid contacts so thatthe front metal grid makes a lower-loss contact to the underlyingsilicon (Figure 1). A traditional uniform emitter is a compromisebetween making low-loss contacts by reducing emitter sheet resistanceand transmitting more photons by increasing the emitter sheetresistance. By selectively decreasing emitter sheet resistance onlyunder the front metal contacts and increasing emitter sheet resistanceelsewhere, one can simultaneously minimize contact-related resistivelosses and maximize photocurrent generation.
The precise localemitter doping required for an efficient selective emitter can be formed by various methods, including deposited dopants, deposited etchants,patterned wet etch masks, spatially-defined ion implantation, etc.Given that most cell manufacturers already use industrial screenprinting for applying front metal grids it is convenient and costeffective for them to use closely related screen printing techniques toform the selective emitter. The key to using low-cost screen printingfor selective emitter processing is to use a high-precision printer that allows one to align the front metal grid to precisely overlay thehighly-doped selective emitter regions. For example, Applied Materials’ Baccini Coating Systems division offers high-volume screen printers with an Esatto upgrade that provides the required precision and repeatability. The cellefficiency gain achieved with selective emitter technology variesdepending on the specifics of the cell, e.g. wafer quality, baselinediffusion process, baseline grid process, etc.; but an efficiency gainof 0.5 % absolute is possible.
Figure 1 The selective emitter is a heavily-doped region placed directly under the metal line.
A key factor in optimizing the selective emitter efficiency gain is are-tuning of the metal grid pattern so that the photocurrent andphotovoltage gains are not negated by lateral “spreading resistance”losses in the now-more-resistive emitter between the grid fingers. There-tuning of the metal grid pattern generally entails decreasing thespacing between grid fingers, hence increasing the total number of gridfingers, which in turn increases the total grid coverage and decreasesthe cell photocurrent. The optimized balance between gains and lossesis easier when using a fine-line metallization technology to make thegrid.
Fine line metallization – defined broadly as methodscapable of forming a continuous high-conductance grid with finger widths below 100 microns – provides stand-alone advantages including loweroptical losses due to metal coverage and lower grid metals costs use due to lower paste consumption, but fine line metallization is ofparticular leverage when combined with selective emitter technology. There are a variety of fine line metallization technologies, includingadvanced screen printing, ink jet printing, aerosol printing,electroless and electroplating, etc. As with selective emitter, giventhat most c-Si cell manufacturers already use industrial screen printing for high-through-put metallization it is convenient and cost effectivefor them to use advanced screen printing techniques such as “doubleprinting” to achieve the desired fine line metallization.
“Doubleprinting” is simply printing a metal grid pattern, then over-printinganother layer of metal exactly on top of the first to achieve a tall,narrow grid so that grid fingers shadow less (due to their being morenarrow) while still conducting well (due to their being taller). Standard one-layer printing requires a relatively wide grid to achieveadequate conductance at typical layer thicknesses. Double printingincreases the total layer thickness so that one can achieve equalconductance with narrower grids (figure 2). Narrow, tall,double-printed grids cover less of the cell’s front surface so the cellhas a higher photocurrent. Double-printing can be used alone todirectly substitute for traditional single printing to provide anefficiency gain of up to 0.25 % absolute, or can be combined withselective emitter technology for overall gains of 0.7 % absolute orhigher.
Figure 2 Decreasing linewidth reduces shadowing of the active area, increasing potential efficiency.
In all cases – selective emitter, fine-line metallization such as doubleprinting, or combinations of selective emitter and fine-linemetallization – an initial material is precisely overcoated with another material to achieve superior results. This precision overcoatingrequires a combination of good-quality initial coating, high-sensitivity detection of the initial material (e.g. the high-conductance selectiveemitter regions), precise alignment of the second patterned coating tothe first, and consistent coating placement; and these requirements must be met on large thin high-value cells. PV equipment providers aredeveloping a wide array of approaches to these challenges.
Further improvements in cell efficiency are being pursued through the use ofinnovative cell structures that place all the contacts on the backsurface of the wafer, eliminating the shadowing effect entirely. Candidate structures include metal wrap through, emitter wrap throughand various integrated back contact structures. These structures imposevarious new requirements on PV tool builders and materials suppliers,e.g. high-speed hole drilling in fragile Si wafers, interdigitated n-and p-type contacts, low-loss interconnection of high-currentall-back-contact cells, etc. The challenge is to deliver efficiencygains while maintaining low cell processing and module assembly costs,and to deliver these gains at ever increasing scale on thinner wafers.
Check back tomorrow for part two, “Thinner Wafers and Higher Throughputs,” of this three part series.